The present invention relates to a method for making semiconductor devices that include dual damascene interconnects.
Dual damascene metal interconnects may enable reliable low cost production of integrated circuits using sub 0.25 micron process technology. The lithographic process used to define dual damascene features can be relatively complex. Unlike conventional processes, which only require etching vias through a dielectric layer, processes for making dual damascene structures also require etching trenches into that layer.
One way to form such a device begins by forming a dual hard mask on top of a dielectric layer prior to patterning the trench and via, as illustrated in FIG. 1a. That figure represents a structure that includes a substrate 10 upon which is formed conductive layer 11, barrier layer 12, dielectric layer 13 (e.g., a polymer based film), silicon dioxide hard mask 14 and silicon nitride hard mask 15. In this process for making a dual damascene structure, a trench is then patterned using conventional lithography steps. Etching the portion of silicon nitride hard mask 15 that the photoresist layer did not protect produces the structure illustrated in FIG. 1b. Silicon dioxide hard mask 14 serves as an etch stop for that process step.
Photoresist layer 16 is then deposited and patterned to define a via, as shown in FIG. 1c. Exposed portions of hard masks 14 and 15 are removed, generating the structure shown in FIG. 1d, followed by etching via 17 partially through dielectric layer 13 to produce the structure shown in FIG. 1e. The portion of silicon dioxide hard mask 14 that is not protected by silicon nitride hard mask 15 is then removed, producing the FIG. 1f structure. Dielectric layer 13 is then further etched to produce the structure shown in FIG. 1g. The exposed portion of barrier layer 12 is then removed, as illustrated in FIG. 1h, to complete via 17 and trench 18. That via and trench may then be filled with a conductive material, e.g, copper, using techniques that are well known to those skilled in the art.
As is apparent from FIGS. 1a-1h, this process leaves little room for error when lining up the mask that will define the via. The alignment budget for that mask is, in essence, dictated by the trench""s width. Unless part of the mask lines up with part of the trench, separation will result between the subsequently formed via and trench, which will yield an inoperable device. Other problems may arise when a polymer based film is used to make the dielectric layer. Because such a film may have relatively poor mechanical properties, structural instability may result. In addition, using such a film may cause via profile degradation. Using a carbon doped oxide instead may enhance the resulting film""s mechanical properties, but may lead to increased etch bias.
Accordingly, there is a need for a process for making a dual damascene interconnect using a multilayer hard mask that will increase the alignment budget for via and trench formation. In addition, there is a need for a process that enhances the mechanical integrity, and the via profile and etch bias, of the resulting interconnect. The method of the present invention provides such a process.